The PLL Demoboard consists of a Crystal Oscillator with a Divider. You can select Reference Frequencies from 250 Hz to 4 kHz. As PLL and VCO, a '4046 is used. Together with three programmable Decade Counters a handy Platform is available to study the nature of a PLL.

Requirements :

Output Frequency : 77.5 kHz

As the Demoboard offers Reference Frequencies of 250Hz, 500 Hz, 1kHz, 2 kHz and 4 kHz we obtain the following values for N:

Reference Frequency	Divider Value (N)	Remarks
250 Hz	310	possible, integer value
500 Hz	155	possible, integer value
1 kHz	77.5	not possible
2 kHz	38.75	not possible
4 kHz	19.375	not possible

As usual there are more possibilities. We will see later, which value to choose and why.

The 'not possible' values may need a different approach: dual modulus prescaler ...

As the Tolerances are high - and depend on the Supply Voltage, the Temperature and other
Parameters, we dimension the VCO to work at 77.5 kHz +/- 20%.

Using the formulas/graphs in the datasheet or this website, we find:

R1 = 100 kΩ
R2 = 120 kΩ
C1 = 1.5 nF

This results in : F_min = 60.8 kHz and F_max = 97.7 kHz whereas 77.5 kHz is somewhere in the middle.

The actual Frequency Range is somehow larger, if the Tuning Voltage goes below 1.1 V or above 3.9 V. Other Solutions are possible as well !!!

The Loop Filter is somehow tricky. If we demand a very fast lock-time, the suppression of the Reference-Clock may be insufficient - and if the Filter is too slow, Oscillation may occur as the Phase shift is to large.

Kφ : Phase Detector Gain • K_VCO : VCO Gain • K_N : Divider Gain, K_N = 1 / N


To proceed further, we have to decide which Phase Detector we use, as their Gain is different.

We choose PD2 and therefore get (from the Datasheet) : Kφ = V_cc / 4 * π , Volt/rad

We decide to use REFCLK = 500 Hz and N = 155.

As ω_n = 10% of REFCLK yields : ω_n = 50 Hz * 2 * π ≈ 314.159 rad/sec.

K_N = 1 / 155 ≈ 0.0064561

K_VCO = 13.185 kHz / V ≈ 82.84379 * 10³ rad/sec/V

Rewriting Formula (1) : (and calculating it)



yields in R₁ * C₁ = 2.1547 * 10^-3

We choose C₁ = 1 µF and R₁ = 2.2 kΩ (other Solutions are also possible !)

Now, let's see what damping factor we have.

Using Formula (2) we calculate ξ = 9.5308 * 10^-3.

Ooooops ! This value is far away of the desired 0.707 !

Using this Filter may result in a very long time to get the VCO locked !

Kφ : Phase Detector Gain • K_VCO : VCO Gain • K_N : Divider Gain, K_N = 1 / N


Again, we choose PD2 and therefore get (from the Datasheet) : Kφ = V_cc / 4 * π , Volt/rad

We decide to use REFCLK = 500 Hz and N = 155.

As ω_n = 10% of REFCLK yields : ω_n = 50 Hz * 2 * π ≈ 314.159 rad/sec.

K_N = 1 / 155 ≈ 0.0064561 and ξ = 0.707

K_VCO = 13.185 kHz / V ≈ 82.84379 * 10³ rad/sec/V

Rewriting Formula (3) :



We choose C₁ = 10 nF and calulate this expression.

We get : R₁ + R₂ = 215.4709 * 10³ Ω.

Rewriting Formula (4) :



Calculating this expression yields : R₂ = -200.7 Ω.

Ooooops ! This is not possible. We decide to increase ξ to ξ = 2.43 as this is still acceptable.

Now, recalculating, we get R₂ = 15 kΩ and therefore R₁ = 200 kΩ.

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LOOPFILTER: C₁ = 1 µF, R₁ = 200 kΩ, R₂ = 15 kΩ, ξ = 2.43, ω_n = 314.159 rad/sec

VCO: R₁ = 100 kΩ, R₂ = 120 kΩ, C₁ = 1.5 nF

This is used in the Project : Homebrew DCF-77 Signal Generator

Requirements :

Output Frequency : 1280 MHz, REFCLK : 10 MHz, N=128

As we use the VCO ROS-1310C+ from MiniCircuits™ we obtain K_VCO = 5 MHz / V

(from Datasheet). This equals K_VCO = 5 MHz / V * 2 * π = 31.41592 * 10⁶ rad/sec/Volt

and ω_n = 10 MHz * 0.1 * 2 * π = 6.2831 * 10⁶ rad/sec.

With N = 128 we obtain K_N = 1/128 ≈ 7.8125 * 10^-3.

Now, as the VCO delivers 1280 MHz at a Tuning Voltage of around 6 Volt, we have no chance

to reach that in using 5 V Logic. We must insert an Amplifier with V_u = 2 (approx.).

Therefore we get another K_Amp = 2.

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