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Reference_100MHz-DIL28.php    8001 Bytes    31-05-2023 10:24:48


A 100 MHz Reference Frequency Source (DIL-28)


made of a HMC1031 and a ABLNO-V-100.000MHz-T2




A 100 MHz Reference Frequency




✈ Circuit Description




What was written here is still true. We squeezed all in a DIL-28 formfactor and improved the documentation (Gerberfiles). So this is one of our new Building Blocks for anything which needs a stable 100 MHz Reference Clock, locked to a stable 10 MHz Reference Clock.

Specifications :

INPUT FREQUENCY10 MHz
OUTPUT FREQUENCY100 MHz
MIN INPUT LEVELtbd
MAX INPUT LEVEL20 dBm
SUPPLY+ 5 V ... 35 V approx. 12 mA



A 100 MHz Reference Frequency in a DIL-28 Formfactor


Instead of a Block-Diagram. The 10 MHz input is at Pin 28, from which it passes a limiter (BAV99, D1). It is then ac-coupled to the HMC1031 (0.1 MHz to 500 MHz Clock Generator with Integer N PLL). This PLL controls a VCXO (ABLNO-V-100.000MHz-T2, Ultra Low Phase Noise XO / VCXO). Power Input is at Pin 1. As there was no space left, a decoupling capacitor must be put externally. Yes, as close to the pin as possible.




✈ Downloads








✈ Performance




A 100 MHz Reference Frequency


The performace is similiar to commercial devices. Once more it must be noted, that the 10 MHz used to lock this thing must be of the best possible quality. What ever garbage rides on the 10 MHz can be seen in the output - multiplied by ten !

As cmos oscillators are rich in harmonics it is also possible to filter out one of them, maybe to clock a dds or as a (clean) lo source.

1 GHz, - 27 dBm
2 GHz, - 56 dBm


Output : 1.35 Vdc, 1.12 Vac
Yes : it's locked.




✈ Share your thoughts



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t1 = 6586 d

t2 = 281 ms

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